The present invention relates to a connection network for providing power, ground and I/O signals to an integrated circuit device and, more particularly, to an integrated circuit device having both C4 and wire bond pads.
Within the integrated circuit industry there is a continuing effort to increase integrated circuit speed as well as device density. As a result of these efforts, there is a trend towards using flip chip technology when packaging complex high speed integrated circuits. Flip chip technology is also known as controlled collapse chip connection (C4) technology. In C4 technology, the integrated circuit die is flipped upside down. This is opposite to how integrated circuits are packaged today using wire bond technology. By flipping the integrated circuit die upside down, solder balls may be used to provide direct electrical connections from the bond pads of the die directly to a corresponding set of pads on a package.
In the following discussion reference will be made to a number of drawings. The drawings are provided for descriptive purposes only and are not drawn to scale.
FIG. 1 illustrates an integrated circuit die 102 that is housed in a cavity 105 of a PGA (Pin Grid Array) package 110. The integrated circuit die includes a semiconductor substrate 103 having a top surface 107 and a back side surface 108. The active regions 109 of the integrated circuit are formed from the top surface 107 of the semiconductor substrate 103. Wire bonds 104 are used to electrically connect integrated circuit connections in integrated circuit die 102 through internal metal interconnects to the pins 106 of package substrate 110. With the trend towards high speed integrated circuits, the inductance generated in the wire bonds 104 of the typical wire-bonded integrated circuit packaging becomes an increasingly significant problem.
FIG. 2 illustrates a C4 mounted integrated circuit die 202 that is electronically coupled to a PGA (Pin Grid Array) package 210 by ball bonds 204. Die 202 includes a semiconductor substrate 203 that has a top surface 208 and a back side surface 207. The active regions 209 of the integrated circuit are formed form the top surface 208 of the semiconductor substrate 203. Because the bond pads of integrated circuit device 202 are located on the top-side surface 208 of the device, the die must be flipped upside down so that it may be attached to package 210. In comparison with the wire bonds 104 of FIG. 1, the ball bonds 204 of integrated circuit device 202 provide more direct electrical connections between the integrated circuit device 202 and the pins 206 of package substrate 210. As a result, the inductance problems associated with typical integrated circuit wire bond packaging technologies are minimized. Unlike wire bond technology, which only allows bonding along the periphery of the integrated circuit die, C4 technology allows connections to be placed anywhere on the integrated circuit die surface. This leads to a much cleaner and more efficient power distribution to the integrated circuit which is another major advantage if C4 technology.
Although the trend in the industry is moving toward using C4 technology when packaging complex high speed integrated circuits, the use of wire bond technology does offer the advantages of lower costs and better availability.
The present invention provides an integrated circuit having a plurality of wire bond pads and a plurality of C4 pads with at least one of the C4 pads being electrically coupled to at least one of the wire bond pads.